The present invention relates to a multiprogrammed data processing system which has the function of interlocking a main storage unit. More particularly, it is directed to a multiprogrammed data processing system which includes a plurality of central processing units (CPUs) that access a main storage unit in common.
Where data stored in a main storage unit is processed by a plurality of CPUs which use the main storage unit in common, it is necessary to ensure that while one CPU is operating with the common data, every other CPU be prevented from improperly rewriting the data.
Hereinafter there will be explained problems in the case where data A stored in a main storage unit is referenced in common in a multiprogrammed data processing system wherein a CPU.sub.1 and a CPU.sub.1 ' accessed the main storage unit in common.
In order to inhibit the common data A from being referenced simultaneously by the two CPUs, data (termed "lock data") B indicating that either CPU is referencing the data A is stored in the main storage unit in advance.
When one central processing unit CPU.sub.1 is to execute a data processing operation with the common data A, the lock data B is checked prior to the execution. If it is indicated in the lock data that the other central processing unit CPU.sub.1 ' is not using the data A, CPU.sub.1 is permitted to refer to the data A, and the use by CPU.sub.1 is indicated in the lock data B. While CPU.sub.1 is performing the processing operation with the data A, reference from CPU.sub.1 ' to the data A is inhibited.
The CPU in the multiprogrammed data processing system consists of an instruction unit, an execution unit, and a storage control unit.
The main storage unit consists of a main storage controller and a main storage.
In a multiprogrammed data processing system, an instruction for checking the lock data B is prepared. (For example, in the "IBM System/370" or a computer having the same architecture, TEST AND SET (TS) instruction corresponds thereto.) The TS instruction is decoded by the instruction unit within the CPU, and a read request for the lock data B is issued to the storage control unit within the CPU. Upon reading out the data B from the main storage controller, the storage control unit transmits it to the execution unit within the CPU, whereupon the execution unit checks the lock data B. Thereafter, a write request for renewed lock data is issued from the execution unit via the storage control unit to the main storage controller.
It takes a considerable period of time for one CPU to read, check, and rewrite the lock data. During this time, there is the possibility that the other CPU will issue a request for altering the lock data and that the main storage unit will accept and execute this request.
In order to prevent such a state to occur, the prior art adopts a measure wherein when one CPU has started the execution of the TS instructions, the other CPU is interlocked with the main storage so as to prevent the other CPU from referencing the main storage.
As methods for applying the interlock with the main storage, there are:
(1) a method wherein the entire main storage is interlocked, and
(2) a method wherein a certain limited region including the lock data is interlocked (Published Unexamined Japanese patent application No. 51-107042).
With the method (1), even if the other CPU issues reference requests to regions different from the region including the lock data, they are all refused and the other CPU is temporarily idle. This is not desirable from the viewpoint of efficiency of system performance. In large-sized computers, in recent years, the reference time to the main storage is an important factor which determines the performance of the system. It is, therefore, desirable to unnecessarily avoid putting the main storage into a state in which it cannot be referenced.
With the method (2), the above problem does not arise. However, each time the main storage is referenced, whether or not the reference is to the region including the lock data must be determined.
In synchronous computers, one operating cycle is usually composed to two timings T.sub.0 and T.sub.1, and the timing at which the request is issued to the main storage is predetermined. In the processing of any request which is not the interlock request, the request is decoded at the timing T.sub.0, the priority level is subsequently determined at the timing T.sub.1, and the request is issued to the main storage at the next timing T.sub.0. The request is accordingly issued every cycle that is determined by the interval of the generation of the timing T.sub.0. However, when the processing in which whether or not the reference is to the region including the lock data is judged is added for every reference to the main storage, the request is decoded at the timing T.sub.0, the priority level is determined at the subsequent timing T.sub.1, the judgement of the lock data is initiated at the next timing T.sub.0, and the request is issued to the main storage at the next timing T.sub.1. In the synchronous computers, the succeeding decode request can be started only at the next timing T.sub.0. Therefore, the request to the main storage is issued at the timing T.sub.1 for an interval of two cycles and the throughput decreases to half.
The present invention has for an object the provision of a multiprogrammed data processing system, wherein the interlock of a main storage is applied to a region limited and wherein in checking if a reference to the main storage from another CPU is to the interlock region, the period of time required for the check is shortened to increase the speed of a request for reference to the main storage.